The present invention relates to a distributed control type electronic switching system and, more particularly, to a distributed control type electronic switching system provided with a plurality of processors that are redundantly structured.
Almost every prior electronic switching system has a centralized control subsystem which performs various control functions on a real time basis with a single centralized processor. However, such a switching system requires a substantial initial investment because it is equipped, from the outset of system installation, with a processor having a processing ability commensurate with the maximum number of lines to be accommodated.
In recent years, as the progress of semiconductor technology has made available for practical use smaller and less expensive general-purpose microprocessors, a linear-growth multiprocessor control subsystem, which can solve the problem of early electronic switching systems by the use of a plurality of microprocessors, can be readily structured. A multiprocessor control subsystem is known, in broad terminology, as a decentralized or distributed control subsystem as opposed to a centralized control subsystem having only one processor, and performs various switching functions in an electronic switching system ranging in capacity from very small to very large. One example of an electronic switching system having such a distributed control subsystem is disclosed in U.S. Pat. No. 4,210,782. In the system disclosed therein, each of the plural distributed signal control processors provided corresponding to the switching network, line circuit, and trunk circuit and which are required to accomplish their control on a real-time basis, is a single processor, so that if one of the signal processors runs into trouble, the corresponding call processing service will inevitably have to be suspended.
To solve this problem, a well known technique is to redundantly structure single devices including the processors. Processors can be redundantly structured by: (1) the "N+1" structure, by which one spare or standby processor is provided for a plurality of regular processors, or (2) the "ACT/STBY" structure, by which a standby processor is provided for every acting processor. These redundant structures can help improve the reliability of the system even in the event of trouble, but they inevitably tend to be uneconomical.